The present invention generally relates to image clock signal generating systems, and more particularly to an image clock signal generating system for an optical scanner.
An optical scanner is used in laser printers, plate making machines, laser facsimile machines, digital copying machines, flying spot scanners and the like. The optical scanner is used to write and/or read information by a light beam.
A laser scanner uses a laser beam to write and/or read information on and/or from a recording medium. Generally, the laser scanner is provided with a deflector such as a polygonal mirror for deflecting a laser beam which is to scan the recording medium. However, it is virtually impossible to keep the scan timing constant for each scan because the rotation of the deflector cannot be maintained perfectly constant and mirror surfaces of the deflector cannot be finished to perfect mirror surfaces. For this reason, a synchronizing signal is required to control the scan timing to an optimum timing.
Conventionally, prior to each scan by the laser beam, the scan is synchronized by detecting the laser beam immediately prior to the scan. The laser beam is detected immediately prior to each scan by a light receiving element which is arranged at a position which is outside an image scan range of the laser beam and leading a start position where the image scan starts. The synchronizing signal is generated based on an output of the light receiving element, and the laser beam is modulated by an image information in synchronism with the synchronizing signal. However, such a synchronization which simply detects the laser beam at one point prior to each scan is insufficient, because the scanning speed is not perfectly constant due to a deviation in the rotational speed of the deflector, a deviation of the characteristic of an f.theta.-lens from an ideal linear characteristic and the like. When the scanning speed is not perfectly constant, the accuracy of the dot arrangement, that is, the printing quality, deteriorates in the case of the laser printer.
Accordingly, methods have been proposed to generate a reference pulse for synchronization at a plurality of points in each scan. For example, a Japanese Laid-Open Patent Application No. 60-10967 proposes a system of generating an image clock signal by use of a grating which is referred to as a slit, grid or scale. On the other hand, a Japanese Laid-Open Patent Application No. 60-75168 proposes a system of generating an image clock signal by use of a concave mirror array and a plurality of small light receiving elements such as pin photodiodes.
In such proposed systems, the reference pulses (pulse train) which are generated for the entire scan length in accordance with the bright and dark arrangement of the grating are shaped in a shaping circuit if necessary, and a phase locked loop (PLL) circuit generates the image clock signal based on the shaped reference pulses. The image clock signal is used to enable and disable the scanning operation of the optical scanner, that is, to enable and disable the print operation of a laser printer, for example.
FIG. 1 shows an example of a conventional PLL circuit. In FIG. 1, a PLL circuit 1 comprises a voltage controlled oscillator (VCO) 2, a frequency divider 3, a phase comparator 4 and a lowpass filter 5 which are connected as shown. A reference pulse signal (synchronizing signal) Pr which is applied to an input terminal 6 is supplied to the phase comparator 4 which compares the phase of the reference pulse signal Pr with the phase of a feedback signal Pf. This feedback signal Pf is output from the frequency divider 3 which frequency-divides an output image clock signal of the VCO 2 by N (that is, multiplies by 1/N). A phase error signal output from the phase comparator 4 is passed through the lowpass filter 5 which eliminates unwanted noise and high-frequency components. An output signal of the lowpass filter 5 is supplied to the VCO 2. Hence, a feedback control is carried out so as to match the phase of the reference pulse signal Pr and the phase of the feedback signal Pf. The VCO 2 thus outputs the image clock signal which is in phase synchronism with the reference pulse signal Pr and has a frequency N times that of the reference pulse signal Pr. According to this PLL circuit 1, it is possible to obtain an image clock signal which follows a change in the scanning speed, that is, a frequency change of the reference pulse signal Pr.
An information which is to be printed is supplied to a driving and modulating circuit from a printer controller or a host machine. The driving and modulating circuit modulates a laser beam by the information in synchronism with the image clock signal which is output from the PLL circuit 1. As a result, it is possible to print with an accurate dot arrangement. In other words, even when the scanning speed deviates due to an unstable rotation of the polygonal mirror or the like during the printing, the modulation timing of the laser beam is controlled depending on the image clock signal, thereby making it possible to appropriately print optically.
But in FIG. 1, the reference pulse signal Pr which is applied to the PLL circuit 1 is generated intermittently. That is, pulses of the reference pulse signal Pr are generated a plurality of times within the scan range (image range) of the laser beam but ceases in the non-scan range (non-image range) of the laser beam as shown in FIG. 2(A). For this reason, in the non-scan range, an oscillation frequency fO of the VCO 2 is the free-running frequency of the VCO 2, and it takes a pull-in time tp for the output signal frequency of the VCO 2 (that is, the PLL circuit 1) to stabilize for use as the image clock signal frequency even when the PLL circuit 1 receives the reference pulse signal Pr. FIG. 2(B) shows the output image clock signal ICLK of the VCO 2.
In addition, the feedback signal Pf which is used for the phase comparison with the reference pulse signal Pr in the phase comparator 4 is obtained by frequency-dividing the output signal of the VCO 2 by N in the frequency divider 3. But since the frequency divider 3 operates constantly, the phase error between the feedback signal Pf and the reference pulse signal Pr which is received as the range changes from the non-scan range to the scan range changes because the phase relationship between the output signal of the VCO 2 and the reference pulse signal Pr cannot be guaranteed in the non-scan range. As a result, not only does the pull-in time tp increase, but the stability of the PLL circuit 1 is affected. That is, a phase error DP is introduced between the reference pulse signal Pr shown in FIG. 3(A) and the feedback signal Pf shown in FIG. 3(B).
Therefore, the PLL circuit 1 suffers a problem in that the oscillation frequency f0 of the VCO 2 deviates in the non-scan range in which the reference pulse signal Pr ceases. It is possible to consider holding the input voltage of the VCO 2 in order to stabilize the output of the VCO 2, but the voltage control is easily affected by a temperature change and is unstable.